Returning to Rivian on the Platform Functional Safety team, working on kernel-level infrastructure for a safety-critical embedded RTOS.
What I worked on
- Kernel benchmarking infrastructure — designed and built a benchmarking harness integrated directly into the RTOS, covering the full kernel surface: context switching, semaphores, IPC/queues, heap allocation, and scheduler selection. Structured so each kernel operation is measured in isolation, with two interchangeable measurement modes — a throughput counter for regression signals and a latency sampler producing cycle distributions (min/median/p99/max).
- Cycle-accurate timing — implemented a timing instrument over hardware performance counters with sub-nanosecond resolution and near-zero overhead, including self-calibration and a cross-thread timestamping mechanism for operations that span context switches.
- Hardware trace validation — validated software timing measurements against non-intrusive hardware trace (Lauterbach TRACE32) to capture execution paths invisible to software counters.
- CI integration — wired the benchmarking harness into CI as a per-build regression gate on pinned hardware, automatically flagging performance regressions against the previous release.
Skills
- RTOS internals: kernel instrumentation, scheduler analysis, deterministic timing
- Hardware: hardware performance counters, non-intrusive hardware trace
- Tooling: Lauterbach TRACE32, JTAG, CI on pinned embedded hardware
- Safety context: functional safety, priority inversion hazards, safety-critical system constraints